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PIC18F86J72/87J72
4. Module: Real-Time Clock and Calendar
(RTCC)
When the RTCC output is enabled (RTCOE = 1 ),
the RTCC module does not override the input
state of RG4.
Work around
Clear the port direction bit associated with the
RG4 pin (TRISG<4>) when the RTCC output to
RG4 is desired.
Affected Silicon Revisions
5. Module: MSSP (I 2 C? Mode)
In Master I 2 C Receive mode, if a Stop condition
occurs in the middle of an address or data
reception, the SCL clock stream will continue
endlessly and the RCEN bit of the SSPCON2
register will remain set improperly. When a Start
condition occurs after the improper Stop condi-
tion, nine additional clocks will be generated
followed by the RCEN bit going low.
Work around
Use low-impedance pull-ups on the SDA line to
A1
X
A3
reduce the possibility of noise glitches that may
trigger an improper Stop event. Use a time-out
event timer to detect the unexpected Stop
condition and subsequently stuck RCEN bit.
Clear the stuck RCEN bit by clearing the SSPEN
bit of SSPCON1.
Affected Silicon Revisions
DS80508C-page 4
A1
X
A3
X
? 2011 Microchip Technology Inc.
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